In recent years, with the improvement (higher processing speed, higher density circuit, or the like) of performance of hardware associated with an information processing apparatus, the amount of data compatible with the hardware (for example, thousands to several gigabytes). Examples of such hardware includes, for example, a network packet processing circuit, a video data encoding/coding circuit, and a database processing circuit.
Also, with the development of semiconductor technology, large-volume data of several gigabytes can be stored in a single chip of large scale integration (LSI), such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA).
As a circuit that maintains large-volume data in such an LSI, an on-chip memory or a register (or flip-flop (FF)) has been used.
Since the on-chip memory has limitation in the number of ports, there is also limitation in the number of processing circuits capable of accessing the on-chip memory simultaneously. Therefore, there is a need to study use of hardware in order to improve processing performance of the hardware.
On the other hand, since the register can have a large number of ports, a large number of processing circuits can access the register simultaneously. Therefore, the register is suitable to improve processing performance of the hardware.
On the other hand, large-volume generally has a data structure. For example, a transmission control protocol (TCP) (IPv4) packet has a data structure as illustrated in FIG. 12. Furthermore, a network packet or a video file even includes information on a data structure as its header.
In the case of processing large-volume data in an LSI or the like, for example, as illustrated in FIG. 13, entire data (M bytes) is stored in a register and access is frequently performed with respect to field data (N bytes ; N<M) arranged at a designated offset.
In this case, it is preferable to access the field data of N bytes from an arbitrary offset in data of M bytes at a time (that is, in one clock cycle) in order to realize flexible and rapid processing.
In FIG. 13, there is an example in which consecutive N-byte data segments (N=4) are accessed from offset 8 bytes in a M-byte data segment.
In order to realize random access with respect to large-volume data, a first register storing the large-volume data (data of an M-byte length) and a second register storing field data (N-byte data) to be processed by a processing circuit are connected to each other through a multiplexer circuit. The multiplexer circuit receives a control signal and switches connection relationship between the first register and the second register to perform loading of data from the first register to the second register or loading of data from the second register to the first register.
However, the circuit amount of the multiplexer circuit that enables random access with respect to the large-volume data increases considerably.